ELEN4012A · FINAL-YEAR CAPSTONE
A routine update is only useful if it reaches the person waiting for it. LightLink explores whether suitable existing power wiring and a local light receiver could carry non-critical messages with fewer interruptions.
POWER LINE COMMUNICATION × VISIBLE LIGHT COMMUNICATION
Existing wires. A small buffer. A different last hop.
THE PROBLEM & OUR APPROACH
Imagine a maintenance team at a fixed receiving point waiting for an update that stops halfway through. Reusing suitable wiring could reduce the need for another cable route, but uneven delivery still has to be managed. This is a proposed use, not a mine-tested service.
For routine maintenance or status messages, a complete update matters more than a link that is fast only some of the time. The proposed route reuses suitable electrical wiring and ends at a dedicated light receiver. Extra equipment is still needed; mine coverage and cost savings have not been demonstrated.
Across 31 laboratory arrival records, PLC gaps reached about 5.46 seconds. A high mean delivery rate did not remove those pauses. Meanwhile, the optical link drains its queue at a limited rate, so both running empty and admitting too much data matter.
A 105,472-byte FIFO stores the reserve. The selected mode starts at the declared 75% fill level and uses occupancy feedback to target 85%. In the integrated comparison it maintained headroom without recorded full-FIFO rejections. A finite reserve still cannot cover every measured interruption.
Compare a six-packet burst with and without storage. Each step represents a VLC opportunity to send up to two packets; these are teaching units, not measured hardware rates.
Send a burst to see the gateway hold data while the light link sends at its own pace.
0 packets lostA buffer buys time; it does not increase VLC capacity, remove electrical interference, or cover an indefinite outage. Once storage fills, excess input is lost in this model. In the real system, backpressure or retries must be handled by the transport and gateway.
Explore buffer size and interference ↓FROM WALL TO LIGHT
PLC brings the data in. A buffer helps manage the handoff. VLC carries it across the optical link.
PLC adapters use the mains wiring as a communication path. Interference can make delivery uneven.
Queued messages wait at the gateway until the optical transmitter is ready to carry them.
An LED carries the encoded message. A photodiode and receiver electronics turn it back into data.
A CLOSER LOOK
Explore the PLC path and gateway through project illustrations, alongside the actual receiver circuit drawings. Tap any image to inspect it.
Two PLC adapters bridge the router and gateway over existing mains wiring. This is a conceptual layout, not a bench photograph.
The gateway holds incoming data and releases it as the optical transmitter becomes ready. Queue sizes here are illustrative.
The photodiode input stage.
The receiver amplifier stage.
PLC equipment, gateway, LED transmitter, and complete setup photographs are awaiting team contributions.
02 / THE BUFFER CHALLENGE
Protect the image without leaving too much data waiting. Three challenges. One shared scoreboard.
Your nickname and scores appear online after three attempts. Use a nickname rather than contact details.
Practice first, or enter a nickname to play the same calm, busy and harsh challenges as everyone else.
Sample crest: Wits University. Tile removal illustrates missing data; this is not an actual transmission of the crest.
Each attempt starts at 1,000 points. Subtract 20 points per percentage point of data unavailable at 60 seconds, and 100 points per second of peak FIFO queue delay. Scores stop at zero. Your ranked score is the rounded average of all three attempts. Your best complete round per nickname is ranked; earlier-started completed rounds break ties.
Everyone uses the same deterministic traces. The server recalculates results from your buffer choices. Overflow and data still waiting at the deadline count toward missing image tiles. Queue delay is estimated from peak queued data ÷ optical drain rate; a larger empty buffer does not inherently slow the link.
60 model seconds play in about 10 seconds on screen. Teaching rates: source 10 kB/s, PLC bursts 40 kB/s, optical drain 12.5 kB/s. These are not measured project rates. The game never controls the rig.
Loading the shared scoreboard…
| Rank | Nickname | Average | Calm | Busy | Harsh |
|---|
PLC INVESTIGATION / REPORT UPDATED 26 OCTOBER 2026
Broken delivery can interrupt a routine message even when average PLC speed is high. The investigation starts with those gaps, then asks how much data to hold in reserve and how to keep that reserve usable.
HOW WE INVESTIGATED THE PROBLEM
Packet captures record when PLC data arrive. Their gaps inform the buffer requirement. A separate integrated comparison then tests five startup and sender-pacing modes with a charger connected, observing useful output and buffer fill.
5,393 seconds of packet arrivals across two laboratories.
The 2.5 s sizing target does not cover every interruption.
103 KiB, with declared 75% startup and 85% occupancy target.
SELECTED TESTED CONFIGURATION
The source adjusts admission to preserve a reserve and leave room for arrivals. It does not change FIFO capacity or the optical clock.
The selected mode delivered 201.24 kbit/s of received payload after the first 5 seconds and held 84.96% mean fill, with no recorded full-FIFO rejections across its three complete captures.
Immediate fixed-rate buffering delivered slightly more payload, but saturated the queue. The selection favours inventory and admission headroom, rather than the highest output alone.
Five modes, with three 60-second repeats each. A 65 W laptop charger was connected, the iron was off, the optical path was 3 cm at 0-degree alignment, and the nominal optical setting was 280 kbit/s.
The PLC characterisation used a TL-PA7017 pair. Integrated tests used TL-PA4010 and TL-WPA4220 adapters. Their advertised link rates are not application payload rates.
Three different quantities: 300 kbit/s is the conservative sizing basis and tested optical maximum; 280 kbit/s is the integrated nominal setting; 201.24 kbit/s is the selected mode's measured received payload.
| Measure | Immediate fixed-rate | Selected gated-feedback |
|---|---|---|
| Mean received payload, after 5 s | 204.91 kbit/s | 201.24 kbit/s |
| Buffer behaviour | Queue saturated | 84.96% mean fill after 5 s |
| Recorded full-FIFO rejections | 19,719 | 0 |
| Zero-output counter windows, after 5 s | 0 / 327 | 5 / 327 |
Rejection counts cover three complete captures per mode, including startup. Received-payload and occupancy summaries exclude the first 5 seconds. Counter windows are observations at the polling resolution, not proof of gap-free output at every instant.
The report pools three repeats per mode and retains zero-output windows. The buffered configurations outperform the tested bypass; the comparison does not isolate FIFO residence from admission and decoder behaviour.
The traces show repeat 2 with startup retained. Gated feedback regulates inventory; immediate feedback underfills, while fixed-rate modes approach full occupancy.
The 2.5 s target uses a 300 kbit/s drain assumption: 37.5 kB/s needs 93.75 kB for 2.5 seconds, within the 110 kB allowance. The implemented 105,472-byte FIFO holds about 2.11 seconds at 75% fill and 2.39 seconds at 85% fill on that assumed basis. Framing and actual transmission timing affect the running drain.
The target comes from retrospective sizing over the 31 arrival records under ideal recovery. It is not independently validated outage coverage or an application-specific delay guarantee. Packet-arrival gaps are not one-way latency. No mine deployment, recorded-speech playback quality, mine-wide coverage or installation savings was demonstrated.
Potential future use is non-critical maintenance or status delivery to a fixed optical receiving point, with site-specific cable, electrical, optical and equipment assessment still required.
Download the reported comparison and context · Versioned data and methods
RECORDED TESTS / 12 OCTOBER 2026
Two views from the actual test and dashboard files. Tap the plots to inspect them.
All three source/received pixel comparisons matched on the local USB → light route. Time includes host pacing and receiver feedback.
Download plotted image results
Buffer occupancy from a PLC-labelled gateway dashboard session. The dashed line marks the configured 75% startup/refill threshold.
Download plotted FIFO samplesImage source: text_image_vlc_demo/tests/highres_live_acceptance.json. FIFO source: vlc_150khz_test/dashboard/results/20261012_174423_6c2ab0/metrics.csv, first 120 seconds with reported occupancy. Repeated values may be dashboard snapshots. This is not a controlled outage sweep or proof of a particular throttle policy.
A separate USB-injected FIFO test at 250,000 bit/s queued 85,800 bytes and drained in 3.485 s. The observed receiver sequence span contained 1,525 valid packets and no internal sequence gaps; initial calibration packets were excluded. This was not physical PLC ingress or website-to-rig validation.
The buffer feedback protocol reports used/free space periodically and supports sender pacing. The later PLC survey and integrated comparison above supersede these extracts for buffer-design evidence. Filtering is a performance option, not a guarantee. These are historical bench results, not live telemetry.
04 / MAKE IT YOURS
Prepare something on your phone, preview what the receiver will see, and explore the transmission journey.
THE PEOPLE BEHIND THE LINK
School of Electrical and Information Engineering
University of the Witwatersrand
SUPERVISOR
POWERLINE COMMUNICATION
VISIBLE LIGHT COMMUNICATION
PLC characterisation: Nduvho E. Ramashia. VLC development: Israel Chiloane. Buffer requirements, integration and integrated analysis were shared. Supervised by Prof. Ling Cheng.
View the project on GitHub ↗
Internet of Light